A conventional clock multiplication circuit obtains the multiplied clock by performing waveform synthesis of multi-phase clocks. Here, the multi-phase clocks mean N sets of clock signals with edges shifted by T/N relative to each other, where T is the period of the multi-phase clocks. The multi-phase clock generation circuit consists of a system using a PLL circuit or a system using a DLL circuit.
In a system using the PLL circuit, a ring oscillator is required for generating the multi-phase clocks. As such, problems occur in that the PLL circuit is adversely affected by low frequency noise inherent to the ring oscillator, and jitter (variance in clock period) may be generated in the multi-phase clocks. For this purpose, it is desirable to use a DLL circuit in order to suppress the jitter of the multiphase clocks.
FIG. 10 is a block diagram showing an example of the configuration of a conventional multi-phase clock generation circuit using a DLL circuit, and FIG. 11 is a timing chart describing the operation in the normal locking state of a conventional multi-phase clock generation circuit, respectively. The multi-phase clock generation circuit in FIG. 10 shows a case of N=10. In FIG. 10, the conventional multi-phase clock generation circuit comprises a phase detector PD3, a charge pump circuit CP3, a capacitor C3 and voltage control delay elements H21–H30. The voltage controlled delay elements H21–H30 are connected in cascade, multi-phase clocks Ck1–Ck10 are output from each of the voltage controlled delay elements H21–H30, a reference clock Sref is input to the voltage controlled delay element H21 on the first stage, and the multi-phase clock Ck10 output from the voltage controlled delay element H30 on the last stage is fed back to the phase detector PD3.
The multi-phase clock Ck10 fed back to the phase detector PD3 is compared with the reference clock Sref in the phase detector PD3, and an Up3 signal or a Down3 signal is output to the charge pump circuit CP3 according to the phase difference between the multi-phase clock Ck10 and the reference clock Sref. In the charge pump circuit CP3, when the Up3 signal is output, charges are accumulated in a capacitor C3, and when the Down3 signal is output, charges accumulated in the capacitor C3 are discharged. The charge pump circuit CP3 generates the control voltage Vc corresponding to the accumulation of charges in the capacitor C3, and outputs this control voltage Vc to each of the voltage controlled delay elements H21–H30.
Here, in each of the voltage controlled delay elements H21–H30, the delay time τ is changed by the control voltage Vc, and the delay time τ of the each of the voltage controlled delay elements H21–H30 is locked to T/10 by matching the phase of the multi-phase clock Ck10 with the phase of the reference clock Sref. As a result, the multi-phase clocks Ck1–Ck10 for ten phases with edges thereof shifted from each other by T/10 can be generated as shown in FIG. 11.
When the delay time τ of each of the voltage controlled delay elements H21–H30 is controlled so that the phase of the multi-phase clock Ck10 matches the phase of the reference clock Sref, the delay time τ of each of the voltage controlled delay elements H21–H30 can be locked not only to T/10, but also to n·T/10 (n: an integer of 2 or more). Thus, when the maximum number τmax of the delay time τ of each of the voltage controlled delay elements H21–H30 exceeds n·T/10, the phase shift of the multi-phase clocks may not be locked to T/10, but may be improperly locked to n·T/10.
FIG. 12 is a timing chart describing the operation in the improper locking state of a conventional multi-phase clock generation circuit. In FIG. 12, though the phase of the multi-phase clock Ck10 matches the phase of the reference clock Sref, the delay time τ of each of the voltage controlled delay elements H21–H30 is locked to 2T/10. As a result, the shift of the edge of the multi-phase clocks Ck1–Ck10 is not locked to T/10, but is improperly locked to 2T/10. When the shift of the edge of the multi-phase clocks Ck1–Ck10 is improperly locked to 2T/10, the desired multiplied clock cannot be acquired.
Thus, in the conventional DLL circuit, improper locking is generally prevented by setting the frequency f (=I/T) of the reference clock Sref to be smaller than 2/(N·τmax), and preventing the possible maximum number τmax of the delay time τ of each of the voltage controlled delay elements H21–H30 from exceeding 2T/10. However, if the frequency f of the reference clock Sref is limited in order to prevent improper locking, circuits which are different from each other must be designed according to the operating frequency, and a problem occurs in that it is difficult to use one DLL circuit in various kinds of applications.
Thus, one object of the present invention is to provide a multi-phase clock generation circuit and a clock multiplication circuit capable of preventing improper locking while mitigating the limitation imposed on the reference clock frequency.